1. Field of the Invention
The present invention generally relates to output circuits, pulse width modulating circuits and semiconductor integrated circuits and, more particularly, to an output circuit for a pulse width modulation integrated circuit (PWMIC) and a pulse width modulating circuit and a semiconductor integrated circuit in which such an output circuit is used.
2. Description of the Related Art
FIG. 1 is a block diagram of a pulse width modulating circuit in which a prior art output circuit is used. A waveform generating circuit 1 outputs a variety of differently-phased waveforms in accordance with an input clock signal. A waveform selecting circuit 2 selects one of the waveforms from the waveform generating circuit 1 based on, for example, an 8-bit data signal and a 2-bit control signal. An output circuit 3 is supplied with the waveform signal selected by the waveform selecting circuit 2 so as to charge or discharge a load capacitor 4 connected to an output terminal OUT in response to a variation in the polarity of the input signal.
FIG. 2 is a circuit diagram showing the construction of the output circuit 3 comprising a semiconductor chip 5 formed of a PMOS transistor P1 and an NMOS transistor N1, a power supply pad 6 for the semiconductor chip 5, a grounding pad 7 for the semiconductor chip 5, an inductance L1 and a resistance R1 of the lead frame connected between the power supply pad 6 and a power supply terminal Vcc, an inductance L2 and a resistance R2 of the PC board wiring connected between the grounding pad 7 and the ground, an output pad 8 connected to the output terminal OUT, and an inverter circuit 9 connected to an input terminal of the semiconductor chip 5.
A description will now be given of the operation of the prior art output circuit.
As shown in FIG. 3, the waveform generating circuit 1 supplied with the clock signal outputs a variety of differently-phased waveform signals. The waveform selecting circuit 2 selects one of the waveform signals from the waveform generating circuit 1 based on, for example, an 8-bit data signal and a 2-bit control signal, and supplies the selected waveform signal to the output circuit 3.
The semiconductor chip 5 of the output circuit 3 operates such that the PMOS transistor P1 conducts and the NMOS transistor N1 does not conduct when a first polarity of the input waveform signal occurs (for example, in response to a rise of the input wave form signal). Thus, the output circuit 3 charges the load capacitor 4 via the inductance L1, the resistance R1, the power supply pad 6, the PMOS transistor P1 and the output pad 8. When the polarity of the input waveform is inverted, that is, when a second polarity different from the first polarity occurs (for example, responsive to a fall of the input waveform signal), the PMOS transistor P1 does not conduct and the NMOS transistor N1 conducts. Thus, the output circuit 3 discharges the load capacitor 4 via the output pad 8, the NMOS transistor N1, the resistor R2 and the inductance L2.
In this case, the input waveform signal IN is subject to ringing due to the inductance L1 and the inductance L2, producing the waveform OUT as shown in FIG. 4. The resonance frequency f0 of ringing is given by f0=1/2 .pi.LC, where L indicates the inductance and C indicates the capacitance of the load capacitor.
The level of ringing is given by Q=2 .pi.f0.times.L/R, where R indicates the on-resistance of the PMOS transistor P1 and the NMOS transistor N1.
When the current driving capability of the PMOS transistor P1 and the NMOS transistor N1 constituting the semiconductor chip 5 in the prior art output circuit is enhanced so as to enable high-speed charging and discharging of the load capacitor 4, the on-resistance of the transistors is decreased so that the level of ringing as shown in FIG. 4 is increased. Such an increase in the level of ringing produces noise in a signal being transmitted, causing a failure in the logic system. It also invites unwanted propagation that is likely to cause a failure in other devices.
The following measures are conceivable to reduce ringing.
(1) Insert a damping resistance in series with the output pad. PA0 (2) Control the input waveform of the output circuit to have a predetermined gradient which reduces a variation per unit period of time in the current level of the input waveform, thus reducing the level of oscillation in the oscillating circuit (through rate control).
The measure (1) is unfavorable in that the resultant output current is attenuated. The measure (2) is also unfavorable in that the output signal is attenuated and high-speed operation is prevented.
It is to be noted that ringing is caused by the inductance of the power source line and the grounding line connected to the pads 6 and 7, respectively, which are connected to the semiconductor chip 5. That is, ringing is unavoidable as long as the charging of the load capacitor 4 takes place via the inductive power source line located outside the semiconductor chip and the discharging thereof takes place via the grounding line also located outside the semiconductor chip.